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Programmable logic Special logic for Data Acquisition or Trigger applications in physics experiments is developed either in ASICs or in Programmable Logic chips. The design methologies are similar: Device-independent high-level design and simulation languages like VHDL Verilog, SystemC are used to design and simulate the electrical behavior prior to a synthesis & routing process which is specific for the chip. Programmable Logic has less on chip gate resources and is inferior ins speed compared to an ASIC however up to 5 Million user gates may be at disposition to be configured into complex logic systems and certain devices reach up to 300 MHz system clock. Programmable logic may also contain embedded ASIC subsystems like processors, network interfaces or bus interfaces or use commercial or free IP software cores to integrate these as subsystems. The programmable logic is usually favored for fast turn-around, low volume (compared to ASIC), online reconfiguration and logic upgrading. It is also the basis for building general purpose electronic cards which can be configured for a variety of different applications ( Our example: PCI-FLIC and its FPGA design environment: Visual HDL / Synfinity / Foundry) FPGA (Field Programmable Gate Arrays) are the most common programmable chips to implement complex logic systems: The binary congfiguration code which contains the routed application is programmed either into an external Prom or an internal Flash ( Antifuse see below) which load these default configurations at power-up. Usually configuration updates can also be loaded dynamically via instrumentation buses like JTAG, I2C, and sometimes via the PCI..bus. The bit code of the internal logic configuration is stored in either SRAM , Flash or an Antifuse layer inside the FPGA chip. Some companies (AMI , Altera, Xilinx) provide services for FPGA to ASIC conversion. FPGAs with Anti-fuses (Actel, Quicklogic) are considered more radiation tolerant due to their radiation hardened latches and do not require verification of configuration as in SRAM based FPGAs, hence they are interesting for FPGA logic in exposed logic of physics experiments. The antifuses configuration technique is a non-volatile, non-backreadable storage requiring no external Prom nor power-up delay and operates at low power consumption. However the programming procedure per chip may take 1/2 hour and the aging properties should be considered.
PLD's are fast ( down to 3.5 ns ) Programmable Logic Devices which include the legacy PAL ( Programmable Logic Array ), GAL (Generic Array Logic), PLA (programmable Logic Array), EPLD ( Electrically Erasable Programmable Logic Device), MAX ( Multi Array Matrix), some of which can be replaced by PEEL Arrays which are Complex PLDs (CPLDs) with advanced architectural features packed into 24, 28 and 44 pin packages. The PEEL Array CPLD architecture combines a large programmable logic array (PLA) with FPGA-like logic cells. Leading vendors for programmable hardware are: Altera, Xilinx, Actel, Lattice, Quicklogic, Cypress, ICT, Texas Instruments Vendor migrations: The programmable logic market is very quickly changing, devices and tools associted with the following names have been stopped or migrated to other names: Waferscale->ST Microelectronics, Vantis->Lattice, Innoveda->Mentor-Graphics, Gatefield->Actel, Dynachip->Xilinx, Viewlogic->Innoveda>Mentor- Graphics, Verisys->?, Veribest->Mentor-Graphics, HyperLynx->Mentor-Graphics, Exemplar->Mentor-Graphics, IKOS->Mentor
terms: PAL ( Programmable Logic Array ), GAL (Generic Array Logic), PLA (programmable Logic Array), EPLD ( Erasable Programmable Logic Device), Electrically Erasable Programmable Logic Device), MAX ( Multi Array Matrix)
More Keywords around programmable logic Stratix: Altera's very high performance FPGA with embedded DSP blocks (hardware cores !), 3.3 Volt I/O based on 0.13 micron SRAM with copper layer. From 10.570 up to 114.000 logic elements, up to 10 Mbit RAM, up to 840 Mbit/s I/O. Up to 28 DSP blocks, supports differential I/O (LVDS, LVPECL, PCML). External memory interfaces to SDRAM (167 MHz), DDR (334 MHz).Embedded SERDES logic supports interface support for high speed I/O: Utopia IV, SPI-4, Phase 2, SFI-4, 10 Gbit Ethernet XSBI, RapidIO, Hyper Transport, all available via IP cores. Signal termination, up to 12 PLLs. Cyclone: Altera. based on Stratix, but low-cost FPGAs with less pin-count, based on SRAM, up to 20.600 Logic Elements (LE), and up 288 kbit RAM, for complex functions. Available are a set op IP's, in particular embedded NIOS processor. Example: EP1C3: 2910 LE's, 60 K bit, 104 user I/O pins, 144 TQFP. -> EP1C6 -> EP1C12-> EP1C20: 20,060 LE's, 288 K bits, 2 PLL's, 301 user I/O 324 or 400 pin FBGA package. ProASIC: Actel. Flash based FPGA like APA075, in particular for large series, on-chip Flashlock to prevent readback. SERDES( serialiser/deserialiser): Lattice ORT82G5 and ORSO82G5 ispLeverCORE: Lattice
IP IP Modules
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FPGA-
field programmable gate arrays